1. Field of the Invention
The present invention relates to a digital to analog (D/A) converter which is required to stabilize the operation and enhance the operation speed.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an example of a conventional D/A converter. FIG. 1 schematically shows a circuit construction of an 8-bit D/A converter disclosed in "An 80-MHz 8-bit CMOS D/A Converter" (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21. NO. 6, DEC. 1986,) FIG. 2 is a flowchart showing the operation of the D/A converter of FIG. 1 from the step of inputting digital data Data to the step of outputting an analog signal OUT. Digital data Data is input to a decoder X 61 on the MSB (Most Significant Bit) side and a decoder Y 62 on the LSB (Least Significant Bit) side. Outputs PX1 to PX4 of the decoder 61 and outputs PY1 to PY4 of the decoder 62 are respectively input to latch circuits 63 and 64. The latch circuits 63 and 64 respectively supply in synchronism with a clock signal CK the latch outputs X1 to X4 and Y1 to Y4 to switch control circuits 65 arranged in a matrix form. The switch control circuit 65, switch 66 and analog signal source 67 constitute a unit cell. With this construction, one of the unit cells is defined corresponding to the input digital data. The switches 66 are respectively controlled by the corresponding switch control circuits 65. According to ON/OFF of the switches 66, the analog signal sources 67 each constructed by a resistor or current source having a predetermined analog value are selectively connected to an output terminal 68 or disconnected therefrom. By effecting a sequence of the above operations, an analog signal OUT corresponding to the digital data Data is derived from the output terminal 68.
FIG. 3 is a timing chart showing the operation of the circuit shown in FIG. 1. In FIG. 3, T11 denotes a time delay from the time the digital data Data is supplied to the decoders 61 and 62 until the outputs PX1 to PX4 and PY1 to PY4 are output; T12, a time delay from the time the outputs X1 to X4 and Y1 to Y4 are supplied from the latch circuits 63 and 64 to the respective switch control circuits 65 until the control signals are output from the switch control circuits 65 to the respective switches 66; and T13, a time delay taken until a preset number of analog sources 67 are connected to the output terminal 68 via the corresponding switches 66. An analog signal reaches a corresponding level. The switches 66 are switched when the delay time T12 has elapsed after the clock signal CK raised. The process time T12+T13 determines the time period TS of the clock signal CK and therefore the delay time T12 limits the enhancement of D/A conversion speed.
FIG. 4 is a circuit diagram of a concrete construction of a 4-bit D/A converter obtained as the simplified construction of the 8-bit D/A converter of FIG. 1. In FIG. 4, the relation between digital data D0, D1 and D2, D3 respectively input to the decoders 62 and 61 and outputs PX1 to PX3 and PY1 to PY3 respectvely output from the decoders 61 and 62 can be attained, for example, as shown in the truth table of FIG. 5. Latch circuits 63 and 64 are constructed by, for example, 2-stage clocked inverters. They respectively output latched outputs X1 to X3 and Y1 to Y3 in response to the rise of the clock signal CK. In FIG. 4, fifteen unit cells 71 which have the same construction as the unit cell of FIG. 1 and arranged in the matrix form are provided.
FIG. 6 is a circuit diagram showing an embodiment of the unit cell shown in FIG. 4. In order to attain the linear increasing characteristic of the output, a NAND.OR circuit 72 shown in FIG. 6 is used in each of the unit cells 71. On/off operation of the switches 73 and 74 are controlled by selectively supplying the outputs X1 to X3 and Y1 to Y3 of the latch circuits 63 and 64 to the predetermined input terminals of the NAND.OR circuit 72. The switch 73 is turned on (the switch 74 is turned off) when an output signal S of the NAND.OR circuit 72 is "1" and a signal S (which is an inverted form of signal S) which is derived via an inverter 75 is "0". An analog current source I is therefore connected to the output terminal 68. Further, when output S is "0" (S is "1"), the switch 73 is turned off (the switch 74 is turned on). Therefore the unit cell 71 is not connected to the output terminal 68.
FIG. 7 is a timing chart showing an example of the operation of the D/A converter of FIG. 4. Assume now that digital data Data is changed from the status "1100" to the status "1011" in the circuit of FIG. 4. In FIG. 7, a timing chart in a case where the digital data Data is changed from "1100" to "1011" is shown. FIGS. 8A and 8B are status diagrams showing the switch image of the matrix of the unit cell 71 obtained in such case. At the time of the status "1100", i.e., in the time period T21, the switch image of the matrix shown in FIG. 8A is obtained. That is, three out of the fifteen switches 74 are turned on and twelve switches 73 are turned on in the unit cell 71. Then, at the time of the status "1011", i.e., in the time period T22, the switch image of the matrix shown in FIG. 8B is obtained. That is, four out of the fifteen switches 74 are turned on and eleven switches 73 are turned on in the unit cell 71.
As described above, the digital data Data is changed from the status "1100" to the status "1011" at the time of rise of the clock signal CK of FIG. 7. This means that the outputs Y1 to Y3 of the latch circuit 64 are changed from "1" to "0" and the output X1 of the latch circuit 63 is changed from "0" to "1". At the time of level change, a phase difference may be caused between the outputs Y1 to Y3 of the latch circuit 64 and the output X1 of the latch circuit 63 in the time period T23 as shown in the timing chart of FIG. 9. The phase difference is caused by a difference in the wiring capacitance for the outputs Y1 to Y3 and the output X1 or a difference in the number of gates of the actually connected unit cells 71. As a result, the outputs Y1 to Y3 may sometimes be changed from "1" to "0" earlier than the output X1 is changed from "0" to "1". At this time, the switch image of the matrix shown in FIG. 10 is obtained and the switches 74 of all of the unit cells are turned on. As a result, the analog signal OUT of the output terminal 68 varies with time t as shown in FIG. 11 when the digital data Data is changed from "1100" to "1011". That is, the number of analog current sources I to be connected to the output terminal 68 is temporarily set to 15.times.I after it has been set to 12.times.I and before it is set to 11.times.I. A so-called glitch occurs. For this reason, a long time delay occurs before the number of analog current sources I to be connected to the output terminal 68 reaches a desired number 11.times.I and noises will occur in this period of time. The same drawback may occur when the digital data Data is changed in a different case.